library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity czc is
port(sz,ks,tz,zt,jk:in std_logic;
ss2:out std_logic;
ss1:out std_logic_vector(7 downto 0);
ss3:out std_logic_vector(6 downto 0));
end czc;
architecture one of czc is
component oneMHZ
port(daclk:in std_logic;
clkout:out std_logic);
end component;
component jifei
port(clk,start,stop,pause,js:in std_logic;
chefei,luc:out integer range 0 to 8000);
end component;
component x
port(daclk:in std_logic;
ascore,bscore:in integer range 0 to 8000;
age,ashi,abai,aqian,bge,bshi,bbai,bqian:out std_logic_vector(3 downto 0));
end component;
component se
port(clk0:in std_logic;
a:out std_logic_vector(2 downto 0));
end component;
component mux8_1
port(c:in std_logic_vector(2 downto 0);
dp:out std_logic;
a1,a2,a3,a4,b1,b2,b3,b4:in std_logic_vector(3 downto 0);
d:out std_logic_vector(3 downto 0));
end component;
component di3_8
port(c0:in std_logic_vector(2 downto 0);
s:out std_logic_vector(7 downto 0));
end component;
component di
port(d1:in std_logic_vector(3 downto 0);
q:out std_logic_vector(6 downto 0));
end component;
signal aa1:std_logic;
signal aa2:std_logic_vector(2 downto 0);
signal aa3,aa4:integer range 0 to 8000;
signal bb1,bb2,bb3,bb4,cc1,cc2,cc3,cc4,d0:std_logic_vector(3 downto 0);
begin
u1:oneMHZ port map(daclk=>sz,clkout=>aa1);
u2:jifei port map(clk=>aa1,start=>ks,stop=>tz,pause=>zt,js=>jk,chefei=>aa3,luc=>aa4);
u3:x port map(ascore=>aa3,bscore=>aa4,daclk=>sz,age=>bb1,ashi=>bb2,abai=>bb3,aqian=>bb4,bge=>cc1,bshi=>cc2,bbai=>cc3,bqian=>cc4);
u4:se port map(clk0=>sz,a=>aa2);
u5:mux8_1 port map(c=>aa2,a1=>bb1,a2=>bb2,a3=>bb3,a4=>bb4,b1=>cc1,b2=>cc2,b3=>cc3,b4=>cc4,dp=>ss2,d=>d0);
u6:di3_8 port map(c0=>aa2,s=>ss1);
u7:di port map(d1=>d0,q=>ss3);
end one;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity czc is
port(sz,ks,tz,zt,jk:in std_logic;
ss2:out std_logic;
ss1:out std_logic_vector(7 downto 0);
ss3:out std_logic_vector(6 downto 0));
end czc;
architecture one of czc is
component oneMHZ
port(daclk:in std_logic;
clkout:out std_logic);
end component;
component jifei
port(clk,start,stop,pause,js:in std_logic;
chefei,luc:out integer range 0 to 8000);
end component;
component x
port(daclk:in std_logic;
ascore,bscore:in integer range 0 to 8000;
age,ashi,abai,aqian,bge,bshi,bbai,bqian:out std_logic_vector(3 downto 0));
end component;
component se
port(clk0:in std_logic;
a:out std_logic_vector(2 downto 0));
end component;
component mux8_1
port(c:in std_logic_vector(2 downto 0);
dp:out std_logic;
a1,a2,a3,a4,b1,b2,b3,b4:in std_logic_vector(3 downto 0);
d:out std_logic_vector(3 downto 0));
end component;
component di3_8
port(c0:in std_logic_vector(2 downto 0);
s:out std_logic_vector(7 downto 0));
end component;
component di
port(d1:in std_logic_vector(3 downto 0);
q:out std_logic_vector(6 downto 0));
end component;
signal aa1:std_logic;
signal aa2:std_logic_vector(2 downto 0);
signal aa3,aa4:integer range 0 to 8000;
signal bb1,bb2,bb3,bb4,cc1,cc2,cc3,cc4,d0:std_logic_vector(3 downto 0);
begin
u1:oneMHZ port map(daclk=>sz,clkout=>aa1);
u2:jifei port map(clk=>aa1,start=>ks,stop=>tz,pause=>zt,js=>jk,chefei=>aa3,luc=>aa4);
u3:x port map(ascore=>aa3,bscore=>aa4,daclk=>sz,age=>bb1,ashi=>bb2,abai=>bb3,aqian=>bb4,bge=>cc1,bshi=>cc2,bbai=>cc3,bqian=>cc4);
u4:se port map(clk0=>sz,a=>aa2);
u5:mux8_1 port map(c=>aa2,a1=>bb1,a2=>bb2,a3=>bb3,a4=>bb4,b1=>cc1,b2=>cc2,b3=>cc3,b4=>cc4,dp=>ss2,d=>d0);
u6:di3_8 port map(c0=>aa2,s=>ss1);
u7:di port map(d1=>d0,q=>ss3);
end one;