2306IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 12, DECEMBER 2003
A
128
EVERSMANN et al. :A
128
m
have been suggested in the literature [7]using the same techno-logical approach as in [4]and [5].However, an extension of this approach to provide two-dimensional sensor arrays with similar pitch is impossible, due to the fact that only one layer (diffusionlines) can be used for interconnect purposes. Consequently, the realization of an architecture which allows row and column se-lection is impossible.
A commercially available sensor array approach for nonin-vasive measurements of neural activity of neural tissue is the multielectrode array (MEA)[8]–[11].MEAs typically consist of less than 100planar metal electrodes on an insulating glass
substrate with a
diameter
m. In case of commercially available MEAs [10],[11],measurement cir-cuitry is usually realized by discrete off-chip components. How-ever, from the literature, approaches for low-density arrays with active on-chip circuity are also known [12]–[14].
Considering the dimensions of neurons, which range from below
10
m is
described [15].
The paper is organized as follows. In Section II, the specifi-cation of the sensor array is derived from application-related bi-ological boundary conditions. Process and technology aspects are briefly discussed in Section III. System and circuit design are considered in Sections IV and V , respectively. Experimental results are revealed in Section VI. Finally, in Section VII, the paper is summarized and future perspectives are projected.
II. S PECIFICATION
The most prominent in vitro applications for high-density sensor arrays are fire-rate analysis of sparse neuron networks and imaging of brain slice activity. These two application cases are schematically sketched in Fig. 2.
In the case of fire-rate analysis [Fig.2(a)],dissociated cells cultured upon the sensor surface reestablish neural networks by the outgrowth of dendrites. For rat neurons (vertebrates)with
a
Fig. 2. Schematic plot describing the most prominent application cases. (a)Networks of dissociated neurons. (b)Brain slices.
diameter of about
10
m pro-vide signals of below 3
mV
2kiloframes per second (kfps),a resolution of the cleft voltage better than
50
m in both directions, and a total sensor area
of at least 1
mm
2308Fig. 3. Schematic cross section of the sensor principle used in this paper. (a)Cross section neuron/sensor.(b)Lumped equivalent circuit
diagram.
Fig. 4. Schematic process flow.
the dielectric must be suitable for cell cultivation, i.e., biocom-patible, it must be chemically inert and leakproof to avoid cor-rosion of the sensor electrode or of the subjacent layers of the CMOS chip. Moreover, it is obvious that the signal-to-noise ratio (SNR)of the structure in Fig. 3improves with increasing electrode capacitance, so that a high dielectric constant and rel-atively low thickness of the sensor dielectric are demanded. The process flow of the extended CMOS process is schemat-ically sketched in Fig. 4[15],[16].We start with a two-metal-layer n-well epi CMOS process optimized for analog applica-tions with minimum gate
length
nm, supply
voltage V , LATID-n-MOS and
LDD-pMOS devices, poly–polycapacitors, and different types of polysilicon resistors. After this standard process (devices,two metal layers, nitride passivation, and tungsten via) is completed, the extra sensor process starts. First, the surface is planarized by a CMP step. An approximately 50-nm-thick Ti/Ptstack is vapor deposited and structured in a liftoff process. This metal stack is used to provide the sensor electrodes and the adhesion layer for the contact
pads.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 12, DECEMBER
2003
Fig. 5. SEM photo of sensor cross section.
As sensor dielectric, a 40-nm-thick stack of 10-nm TiO
, 5-nm ZrO
C to avoid damage of the
metallization layers below. On the adhesion layer of the bond pads, the dielectric is removed by a reactive ion etch [Fig.4(c)].A 400-nm-thick Au layer is vapor deposited on the Pt pad and structured using a liftoff process [Figs.4(d)and (e)].
A scanning electron microscope (SEM)photo of a cross sec-tion of the complete sensor with dielectric, electrode, and tran-sistor after completion of the process is shown in Fig. 5.
IV . S YSTEM S ETUP AND C HIP A RCHITECTURE
In Fig. 6, system setup and chip architecture are depicted. The monolithically integrated sensor array consists of
128
/
converters are converted by 16
analog-to-digital converters (ADCs)with an effective reso-lution above 8bit, which are part of a Gage [17]PC-based measurement system.
The resulting data rate amounts to 32MS/s.A user interface program sorts and represents the acquired data. Moreover, this interface allows controlling timing of the applied control sig-nals, the number of frames per calibration, and the power-up and
EVERSMANN et al. :A
128
during an action potential. In order to calculate the
transfer
function
to the gate voltage
of
2310IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 12, DECEMBER
2003
Fig. 7. Illustration. (a)Radial incremental equivalent circuit of neuron, cleft, and electrode. (b)Corresponding matrix
description.
Fig. 8. (a)Schematic overview of signal path, transfer functions, and noise contributions. (b)Gate-referred equivalent schematic.
is derived as a function of the distance of the center, i.e., the
radius
being the capacitances of the cell membrane and
electrode per area, respectively. The resistance of the electrolyte
is in the
cleft
, and from derived from the resistance of the
electrolyte,
. The values of conductivity and the thickness of the
cleft
capacitances per area are calculated on the basis of the values for the lumped
parameters
noise.
These signals are transformed via the transfer
function
EVERSMANN et al. :A
128
128columns) , the band-
width
needs to be at least 2.8MHz. Noise contributions from the readout
amplifier,
and
converter, and buffer, and the transfer
function with required
bandwidth
is m m
m. Circular sensor electrodes are used
with a diameter of
4.5
m for this process
[19]and a gate area of
11
is selected by closing the related
switch
is closed, so that the associated sensor
transistor forces a current through the row line and the selected
transistor
is opened again and a voltage related to the cali-bration current is stored on the gate node
of
2312IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 12, DECEMBER
2003
Fig. 10. (a)Circuit diagram of complete signal path with details in (b)and (c).(b)Quasi-differential stage in readout amplifier. (c)Output driver and I /V conversion.
switch-off process is approximately equal for all pixels. More-over, the effect of the charge injection on the gate voltage is alleviated due to the large capacitance of the electrode, so that this effect can be neglected in our discussion. The procedure is performed for all rows in parallel, columns are selected subsequently. As result, all sensor transistors within a row provide the same current when selected for readout (i.e.,
with
in Fig. 9(b).
This compensation technique has been motivated here by considering threshold voltage mismatch only. This is rea-sonable, since for low and medium gate voltages, the total transistor drain current mismatch is dominated by threshold voltage mismatch [19].However, at this point, we like to mention that the applied compensation technique compensates for the variations of all sensor transistor parameters which contribute to its drain current mismatch.
The discussion above also reveals that a current mode readout technique is applied. This is mandatory to meet the required pixel bandwidth, since the influence of the parasitic capaci-tances of row signal line and
switches
and
devices
via an external voltage source.
A fast pseudodifferential input stage
[
,
where
EVERSMANN et al. :A
128
5.2mm. After
sawing, the chips are die bonded with a heat-conducting ad-hesive into a ceramic CPGA package and bonded with alu-minum wire. The cultivation chamber is glued with silicone to the package and the interspace volume with the bond wires is filled with epoxy resin.
In Fig. 12, the schematic setup of sensor chip with data acqui-sition system, electrolyte, potentiostat, and electrophysiological reference setup is illustrated. The potentiostat is used to adjust the potential of the electrolyte to the value of a programmable off-chip reference
voltage
is
chosen so that the voltage drop across the sensor dielectric is low, in order not to avoid electrical stress. The electrolyte can be AC modulated with a test signal to allow electrical testing of the sensors of the array.
The electrophysiological setup allows the creation of an in-tracellular contact for cell stimulation purposes and for intracel-lular measurements. This option is provided for reference pur-poses to compare extracellular and intracellular activity.
Photos of the complete setup, the package, and neurons in culture are presented in Fig. 13. A. Electrical Testing
For electrical tests of the chip, the electrolyte on top of the sensor array is sinusoidally modulated with an amplitude of ap-proximately 5
mV
2314IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 12, DECEMBER
2003
Fig. 14. Measured signals of different pixels within a column during test modulation of the electrolyte with 2
mV
, intracellular potential
V , and extracellular potential
V
VII. I V
I VE
EVERSMANN et al. :A
128
2316Peter Fromherz received the Ph.D. degree in phys-ical chemistry in 1969from the University Marburg, Marburg, Germany.
He was a Postdoctoral Fellow at the Max Planck Institute for Biophysical Chemistry at Goettingen, Germany. He became a full Professor for Exper-imental Physics at the University of Ulm, Ulm, Germany, in 1981. In 1994, he was elected as a Scientific Member of the Max Planck Society and joined the Max Planck Institute for Biochemistry in Martinsried/Munich.Currently, he is Director at
the Max Planck Institute for Biochemistry and Professor for Biophysics at the Technical University Munich, Munich, Germany.
Dr. Fromherz is a member of the Academy of Sciences of Berlin and Heidel-berg,
Germany.
Matthias Merz received the degree in physics (Diplom)from the University of Ulm, Ulm, Ger-many in 1999. He is currently working toward the Ph.D. degree at the Max Planck Institute for Biochemistry, Martinsried, Germany, where he studies the growth of topologically defined neuronal networks that are controlled by silicon
chips.
Markus Brenner received the Master of Physics de-gree from the University of Ulm, Ulm, Germany, in 1996and the Ph.D. degree from the Technical Uni-versity of Munich, Munich, Germany, in 2001, both for work done at the Membrane and Neurophysics department of the Max Planck Institute for Biochem-istry, Martinsried, on interfacing neurons with indus-trially made neurochip-arrays of 2048sensors.
He is currently working as an Embedded Software Architect for Siemens Corporate Technology,
Munich.
Matthias Schreiter received the degree in electrical engineering from Dresden University of Technology, Dresden, Germany, in 1996.
He joined the Corporate Research Department of Siemens, Munich, Germany, in 1996, where he worked on material and process development of functional thin films for integrated piezoelectric and pyroelectric
devices.
Reinhard Gabl received the M.S. and Ph.D. degrees in physics from the University of Innsbruck, Inns-bruck, Austria, in 1995and 1999, respectively.
From 1999to 2001, he was with Infineon Technologies AG, Munich, Germany, working on simulations, modeling, design, and technology development of various silicon devices, including RF-PIN, varactor and Schottky diodes, MOS transis-tors, and high-power RF-transistors. Since 1991, he has been with the Corporate Technology Department of Siemens AG, Munich, leading a project team
specializing in functional thin films on silicon. His current interests cover the combination of silicon devices, particularly MEMS with new materials, as well as the research and development of novel MEMS sensors and sensor arrays for utilization in gas and
biodetection.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 12, DECEMBER
2003
Kurt Plehnert received the Dipl.Ing. degree in me-chanical and production engineering from the Uni-versity of Dortmund, Dortmund, Germany, in 1972. Since then, he has been with Siemens Corporate Technology, Munich, Germany. He works in the field of process development with emphasis on photo lithography and thin film
technology.
Michael Steinhauser received the Dipl.-Chem. de-gree and the Dr.rer.nat. degree from the Ludwig Max-imilian University of Munich, Munich, Germany, in 1980and 1987, respectively.
He joined Siemens, Munich, in October 1986, where he is working on the development of thin film modules and sensors. Currently, he is with Siemens Corporate Technology, Design to Prototype Department, where he is engaged in the development of plasmaetch, wetetch, and electroplating
processes.
Gerald Eckstein received the diploma degree in solid state chemistry from the University of Siegen, Siegen, Germany, in 1996, and the Ph.D. degree in materials science from the University of Erlangen-Nuremberg, Erlangen, Germany, in 2001. He joined the Corporate Technology Department of Siemens AG, Munich, Germany, in 2001, where he has been involved in back-end processes and pack-aging technologies of
biosensors.
Doris Schmitt-Landsiedel received the Dipl.Ing. degree in electrical engineering from the Technical University of Karlsruhe, Karlsruhe, Germany, the diploma in physics from the University of Freiburg, Freiburg, Germany, and the Dr.rer.nat. degree from the Technical University of Munich, Munich, Germany.
Following some research projects on semicon-ductor lasers and nonlinear optics, she joined the Corporate Research and Development Department of Siemens AG, Munich, in 1981. There she worked
on scaling problems in MOS devices and on the design of high-speed logic and SRAM circuits. From 1989, she was Section Manager of a group of projects in future generation memory design, analog and digital CMOS and BICMOS circuits, and design-based yield analysis. Since 1996, she has been a Professor of electrical engineering and Director of the Institute for Technical Electronics at the Technical University of Munich. Her research interests are in mixed signal and low-power circuits design, failure analysis and design for manufacturability, and sensors on silicon.
EVERSMANN et al. :A
128
2306IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 12, DECEMBER 2003
A
128
EVERSMANN et al. :A
128
m
have been suggested in the literature [7]using the same techno-logical approach as in [4]and [5].However, an extension of this approach to provide two-dimensional sensor arrays with similar pitch is impossible, due to the fact that only one layer (diffusionlines) can be used for interconnect purposes. Consequently, the realization of an architecture which allows row and column se-lection is impossible.
A commercially available sensor array approach for nonin-vasive measurements of neural activity of neural tissue is the multielectrode array (MEA)[8]–[11].MEAs typically consist of less than 100planar metal electrodes on an insulating glass
substrate with a
diameter
m. In case of commercially available MEAs [10],[11],measurement cir-cuitry is usually realized by discrete off-chip components. How-ever, from the literature, approaches for low-density arrays with active on-chip circuity are also known [12]–[14].
Considering the dimensions of neurons, which range from below
10
m is
described [15].
The paper is organized as follows. In Section II, the specifi-cation of the sensor array is derived from application-related bi-ological boundary conditions. Process and technology aspects are briefly discussed in Section III. System and circuit design are considered in Sections IV and V , respectively. Experimental results are revealed in Section VI. Finally, in Section VII, the paper is summarized and future perspectives are projected.
II. S PECIFICATION
The most prominent in vitro applications for high-density sensor arrays are fire-rate analysis of sparse neuron networks and imaging of brain slice activity. These two application cases are schematically sketched in Fig. 2.
In the case of fire-rate analysis [Fig.2(a)],dissociated cells cultured upon the sensor surface reestablish neural networks by the outgrowth of dendrites. For rat neurons (vertebrates)with
a
Fig. 2. Schematic plot describing the most prominent application cases. (a)Networks of dissociated neurons. (b)Brain slices.
diameter of about
10
m pro-vide signals of below 3
mV
2kiloframes per second (kfps),a resolution of the cleft voltage better than
50
m in both directions, and a total sensor area
of at least 1
mm
2308Fig. 3. Schematic cross section of the sensor principle used in this paper. (a)Cross section neuron/sensor.(b)Lumped equivalent circuit
diagram.
Fig. 4. Schematic process flow.
the dielectric must be suitable for cell cultivation, i.e., biocom-patible, it must be chemically inert and leakproof to avoid cor-rosion of the sensor electrode or of the subjacent layers of the CMOS chip. Moreover, it is obvious that the signal-to-noise ratio (SNR)of the structure in Fig. 3improves with increasing electrode capacitance, so that a high dielectric constant and rel-atively low thickness of the sensor dielectric are demanded. The process flow of the extended CMOS process is schemat-ically sketched in Fig. 4[15],[16].We start with a two-metal-layer n-well epi CMOS process optimized for analog applica-tions with minimum gate
length
nm, supply
voltage V , LATID-n-MOS and
LDD-pMOS devices, poly–polycapacitors, and different types of polysilicon resistors. After this standard process (devices,two metal layers, nitride passivation, and tungsten via) is completed, the extra sensor process starts. First, the surface is planarized by a CMP step. An approximately 50-nm-thick Ti/Ptstack is vapor deposited and structured in a liftoff process. This metal stack is used to provide the sensor electrodes and the adhesion layer for the contact
pads.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 12, DECEMBER
2003
Fig. 5. SEM photo of sensor cross section.
As sensor dielectric, a 40-nm-thick stack of 10-nm TiO
, 5-nm ZrO
C to avoid damage of the
metallization layers below. On the adhesion layer of the bond pads, the dielectric is removed by a reactive ion etch [Fig.4(c)].A 400-nm-thick Au layer is vapor deposited on the Pt pad and structured using a liftoff process [Figs.4(d)and (e)].
A scanning electron microscope (SEM)photo of a cross sec-tion of the complete sensor with dielectric, electrode, and tran-sistor after completion of the process is shown in Fig. 5.
IV . S YSTEM S ETUP AND C HIP A RCHITECTURE
In Fig. 6, system setup and chip architecture are depicted. The monolithically integrated sensor array consists of
128
/
converters are converted by 16
analog-to-digital converters (ADCs)with an effective reso-lution above 8bit, which are part of a Gage [17]PC-based measurement system.
The resulting data rate amounts to 32MS/s.A user interface program sorts and represents the acquired data. Moreover, this interface allows controlling timing of the applied control sig-nals, the number of frames per calibration, and the power-up and
EVERSMANN et al. :A
128
during an action potential. In order to calculate the
transfer
function
to the gate voltage
of
2310IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 12, DECEMBER
2003
Fig. 7. Illustration. (a)Radial incremental equivalent circuit of neuron, cleft, and electrode. (b)Corresponding matrix
description.
Fig. 8. (a)Schematic overview of signal path, transfer functions, and noise contributions. (b)Gate-referred equivalent schematic.
is derived as a function of the distance of the center, i.e., the
radius
being the capacitances of the cell membrane and
electrode per area, respectively. The resistance of the electrolyte
is in the
cleft
, and from derived from the resistance of the
electrolyte,
. The values of conductivity and the thickness of the
cleft
capacitances per area are calculated on the basis of the values for the lumped
parameters
noise.
These signals are transformed via the transfer
function
EVERSMANN et al. :A
128
128columns) , the band-
width
needs to be at least 2.8MHz. Noise contributions from the readout
amplifier,
and
converter, and buffer, and the transfer
function with required
bandwidth
is m m
m. Circular sensor electrodes are used
with a diameter of
4.5
m for this process
[19]and a gate area of
11
is selected by closing the related
switch
is closed, so that the associated sensor
transistor forces a current through the row line and the selected
transistor
is opened again and a voltage related to the cali-bration current is stored on the gate node
of
2312IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 12, DECEMBER
2003
Fig. 10. (a)Circuit diagram of complete signal path with details in (b)and (c).(b)Quasi-differential stage in readout amplifier. (c)Output driver and I /V conversion.
switch-off process is approximately equal for all pixels. More-over, the effect of the charge injection on the gate voltage is alleviated due to the large capacitance of the electrode, so that this effect can be neglected in our discussion. The procedure is performed for all rows in parallel, columns are selected subsequently. As result, all sensor transistors within a row provide the same current when selected for readout (i.e.,
with
in Fig. 9(b).
This compensation technique has been motivated here by considering threshold voltage mismatch only. This is rea-sonable, since for low and medium gate voltages, the total transistor drain current mismatch is dominated by threshold voltage mismatch [19].However, at this point, we like to mention that the applied compensation technique compensates for the variations of all sensor transistor parameters which contribute to its drain current mismatch.
The discussion above also reveals that a current mode readout technique is applied. This is mandatory to meet the required pixel bandwidth, since the influence of the parasitic capaci-tances of row signal line and
switches
and
devices
via an external voltage source.
A fast pseudodifferential input stage
[
,
where
EVERSMANN et al. :A
128
5.2mm. After
sawing, the chips are die bonded with a heat-conducting ad-hesive into a ceramic CPGA package and bonded with alu-minum wire. The cultivation chamber is glued with silicone to the package and the interspace volume with the bond wires is filled with epoxy resin.
In Fig. 12, the schematic setup of sensor chip with data acqui-sition system, electrolyte, potentiostat, and electrophysiological reference setup is illustrated. The potentiostat is used to adjust the potential of the electrolyte to the value of a programmable off-chip reference
voltage
is
chosen so that the voltage drop across the sensor dielectric is low, in order not to avoid electrical stress. The electrolyte can be AC modulated with a test signal to allow electrical testing of the sensors of the array.
The electrophysiological setup allows the creation of an in-tracellular contact for cell stimulation purposes and for intracel-lular measurements. This option is provided for reference pur-poses to compare extracellular and intracellular activity.
Photos of the complete setup, the package, and neurons in culture are presented in Fig. 13. A. Electrical Testing
For electrical tests of the chip, the electrolyte on top of the sensor array is sinusoidally modulated with an amplitude of ap-proximately 5
mV
2314IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 12, DECEMBER
2003
Fig. 14. Measured signals of different pixels within a column during test modulation of the electrolyte with 2
mV
, intracellular potential
V , and extracellular potential
V
VII. I V
I VE
EVERSMANN et al. :A
128
2316Peter Fromherz received the Ph.D. degree in phys-ical chemistry in 1969from the University Marburg, Marburg, Germany.
He was a Postdoctoral Fellow at the Max Planck Institute for Biophysical Chemistry at Goettingen, Germany. He became a full Professor for Exper-imental Physics at the University of Ulm, Ulm, Germany, in 1981. In 1994, he was elected as a Scientific Member of the Max Planck Society and joined the Max Planck Institute for Biochemistry in Martinsried/Munich.Currently, he is Director at
the Max Planck Institute for Biochemistry and Professor for Biophysics at the Technical University Munich, Munich, Germany.
Dr. Fromherz is a member of the Academy of Sciences of Berlin and Heidel-berg,
Germany.
Matthias Merz received the degree in physics (Diplom)from the University of Ulm, Ulm, Ger-many in 1999. He is currently working toward the Ph.D. degree at the Max Planck Institute for Biochemistry, Martinsried, Germany, where he studies the growth of topologically defined neuronal networks that are controlled by silicon
chips.
Markus Brenner received the Master of Physics de-gree from the University of Ulm, Ulm, Germany, in 1996and the Ph.D. degree from the Technical Uni-versity of Munich, Munich, Germany, in 2001, both for work done at the Membrane and Neurophysics department of the Max Planck Institute for Biochem-istry, Martinsried, on interfacing neurons with indus-trially made neurochip-arrays of 2048sensors.
He is currently working as an Embedded Software Architect for Siemens Corporate Technology,
Munich.
Matthias Schreiter received the degree in electrical engineering from Dresden University of Technology, Dresden, Germany, in 1996.
He joined the Corporate Research Department of Siemens, Munich, Germany, in 1996, where he worked on material and process development of functional thin films for integrated piezoelectric and pyroelectric
devices.
Reinhard Gabl received the M.S. and Ph.D. degrees in physics from the University of Innsbruck, Inns-bruck, Austria, in 1995and 1999, respectively.
From 1999to 2001, he was with Infineon Technologies AG, Munich, Germany, working on simulations, modeling, design, and technology development of various silicon devices, including RF-PIN, varactor and Schottky diodes, MOS transis-tors, and high-power RF-transistors. Since 1991, he has been with the Corporate Technology Department of Siemens AG, Munich, leading a project team
specializing in functional thin films on silicon. His current interests cover the combination of silicon devices, particularly MEMS with new materials, as well as the research and development of novel MEMS sensors and sensor arrays for utilization in gas and
biodetection.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 12, DECEMBER
2003
Kurt Plehnert received the Dipl.Ing. degree in me-chanical and production engineering from the Uni-versity of Dortmund, Dortmund, Germany, in 1972. Since then, he has been with Siemens Corporate Technology, Munich, Germany. He works in the field of process development with emphasis on photo lithography and thin film
technology.
Michael Steinhauser received the Dipl.-Chem. de-gree and the Dr.rer.nat. degree from the Ludwig Max-imilian University of Munich, Munich, Germany, in 1980and 1987, respectively.
He joined Siemens, Munich, in October 1986, where he is working on the development of thin film modules and sensors. Currently, he is with Siemens Corporate Technology, Design to Prototype Department, where he is engaged in the development of plasmaetch, wetetch, and electroplating
processes.
Gerald Eckstein received the diploma degree in solid state chemistry from the University of Siegen, Siegen, Germany, in 1996, and the Ph.D. degree in materials science from the University of Erlangen-Nuremberg, Erlangen, Germany, in 2001. He joined the Corporate Technology Department of Siemens AG, Munich, Germany, in 2001, where he has been involved in back-end processes and pack-aging technologies of
biosensors.
Doris Schmitt-Landsiedel received the Dipl.Ing. degree in electrical engineering from the Technical University of Karlsruhe, Karlsruhe, Germany, the diploma in physics from the University of Freiburg, Freiburg, Germany, and the Dr.rer.nat. degree from the Technical University of Munich, Munich, Germany.
Following some research projects on semicon-ductor lasers and nonlinear optics, she joined the Corporate Research and Development Department of Siemens AG, Munich, in 1981. There she worked
on scaling problems in MOS devices and on the design of high-speed logic and SRAM circuits. From 1989, she was Section Manager of a group of projects in future generation memory design, analog and digital CMOS and BICMOS circuits, and design-based yield analysis. Since 1996, she has been a Professor of electrical engineering and Director of the Institute for Technical Electronics at the Technical University of Munich. Her research interests are in mixed signal and low-power circuits design, failure analysis and design for manufacturability, and sensors on silicon.
EVERSMANN et al. :A
128